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NCP5217A Single Synchronous Step-Down Controller
The NCP5217A is a synchronous step-down controller for high performance systems battery-power systems. The NCP5217A includes a high efficiency PWM controller. A pin is provided to enable or disable forced PWM mode of operation. An internal power good voltage monitor tracks the SMPS output. NCP5217A also features soft-start sequence, UVLO for VCC and switcher, overvoltage protection, overcurrent protection, undervoltage protection and thermal shutdown. The IC is packaged in QFN14.
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N5217 ALYWG G
* * * * * * * * * * * * * * * *
0.8% accuracy 0.8 V Reference 4.5 V to 27 V Battery/Adaptor Voltage Range Adjustable Output Voltage Range: 0.8 V to 3.3 V Selectable Power Saving Mode / Force PWM Mode Lossless Inductor Current Sensing Programmable Transient-Response-Enhancement (TRE) Control Programmable Adaptive Voltage Positioning (AVP) Input Supply Feedforward Control Internal Soft-Start Integrated Output Discharge (Soft-Stop) Build-in Adaptive Gate Drivers PGOOD Indication Overvoltage, Undervoltage and Overcurrent Protections Thermal Shutdown QFN14 Package These Devices are Pb-Free and are RoHS Compliant
QFN14 CASE 485AL
A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
EN_SKIP 1 CS+ CS-/Vo COMP FB PGOOD 2 3 4 5 6 7 AGND 8 PGND BST 14 13 DH 12 SWN 11 IDRP/OCP 10 VCC 9 DL/TRESET
Typical Applications
* Notebook Application * System Power
QFN14 (Top View)
ORDERING INFORMATION
Device NCP5217AMNTXG Package QFN16 (Pb-Free) Shipping 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2009
August, 2009 - Rev. 1
1
Publication Order Number: NCP5217A/D
NCP5217A
ENABLE FPWM SKIP IDRP/OCP Detection Over Current Detector CS+ 2 + - CS-/Vo 3 CDIFF Current Sense Amplifier PGH NCP5217A 12 SWN AVP Control 13 DH Thermal Shutdown 14 BST
EN_SKIP
1
Level Control
VREF+10%
+ - +
DISCH
PGL
Control Logic, Protection, RAMP
OSC 11 UVLO Control VCC 10 VCC IDRP/OCP
COMP
4 VREF + - Error Amplifier
VREF-10% VREF-20%
- + - + OVP UVP
Generator and PWM Logic
FB
5 VREF+15%
- OC & TRE Detection
PGOOD
6
PGOOD
9
DL/TRESET
AGND
7
8
PGND
Figure 1. Block Diagram
+5V EN_SKIP 1 EN_SKIP 2 3 4 5 PGOOD 6 CS+ CS-/Vo COMP FB PGOOD AGND 7 NCP5217A QFN14 14 BST DH 13 SWN 12 IDRP/OCP 11 VCC 10 DL/TRESET PGND 8 9 PGND VOUT
VIN
Figure 2. Typical Application Circuit
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NCP5217A
PIN FUNCTION DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol EN_SKIP CS+ CS-/Vo COMP FB PGOOD AGND PGND DL/TRESET VCC IDRP/OCP SWN DH BST Description This pin serves as two functions. Enable: Logic control for enabling the switcher. SKIP: Power saving mode (Skip and Force PWM) programmable pin. Inductor current differential sense non-inverting input. Inductor current differential sense inverting input. Output of the error amplifier. Output voltage feed back. Power good indicator of the output voltage. High impendence (open drain) if power good (in regulation). Low impendence if power not good. Analog ground. Ground reference and high-current return path for the bottom gate driver. Gate driver output of bottom N-channel MOSFET. It also has the function for TRESET. Supply for analog circuit and bottom gate driver. Over current protection and Droop Voltage programmable pin. Switch node between the top MOSFET and bottom MOSFET. Gate driver output of the top N-channel MOSFET. Top gate driver input supply, a bootstrap capacitor connection between SWN and this pin.
ABSOLUTE MAXIMUM RATINGS
Rating VCC Power Supply Voltage to AGND High-side Gate Drive Supply: BST to SWN High-side Gate Drive Voltage: DH to SWN Low-side Gate Drive Supply: VCC to PGND Low-side Gate Drive Voltage: DL to PGND Input / Output Pins to AGND Switch Node SWN High-Side Gate Drive/Low-Side Gate Drive Outputs PGND Thermal Characteristics Thermal Resistance Junction-to-Ambient (QFN14 Package) Operating Junction Temperature Range (Note 1) Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level Symbol VCC VBST-VSWN, VDH-VSWN, VCC-VPGND, VDL-VPGND, VIO VSWN DH, DL VPGND RqJA_QFN14 TJ TA Tstg MSL Value -0.3, 6.0 -0.3, 6.0 Unit V V
-0.3, 6.0 -5 V (< 100 ns) 30 V -3(DC) -0.3, 0.3 48 -40 to + 150 - 40 to + 85 - 55 to +150 1
V V V V C/W C C C -
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. 1. Internally limited by thermal shutdown, 150C min.
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NCP5217A
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 5 V, TA = -40C to 85C, unless other noted)
Characteristics SUPPLY VOLTAGE Input Voltage VCC Operating Voltage SUPPLY CURRENT VCC Quiescent Supply Current in FPWM operation VCC Quiescent Supply Current in Power Saving Operation VCC Shutdown Current BST Quiescent Supply Current in FPWM operation BST Quiescent Supply Current in power-saving operation BST Shutdown Current dV/dt on VCC VOLTAGE-MONITOR Rising VCC Threshold VCC UVLO Hysteresis Power Good High Threshold Power Good High Hysteresis Power Good Low Threshold Power Good Low Hysteresis Power Good High Delay Power Good Low Delay Output Overvoltage Rising Threshold Overvoltage Fault Propagation Delay Output Undervoltage Trip Threshold Output Undervoltage Protection Blanking Time REFERENCE OUTPUT Internal Reference Voltage OSCILLATOR Operation Frequency FSW 270 300 330 kHz VREF 0.7936 0.8 0.8064 V VCCth+ VCCHYS VPGH VPGH_HYS VPGL VPGL_HYS Td_PGH Td_PGL OVPth+ OVPTblk UVPth UVPTblk With respect to Error Comparator Threshold of 0.8 V FB forced 2% above trip threshold With respect to Error Comparator Threshold of 0.8 V 75 - 110 PGOOD in from higher Vo (PGOOD goes high) PGOOD high hysteresis (PGOOD goes low) PGOOD in from lower Vo (PGOOD goes high) PGOOD low hysteresis (PGOOD goes low) 80 Wake Up 4.05 200 105 4.25 275 110 5 85 -5 150 1.5 115 1.5 80 8/fSW 85 - 120 90 4.48 400 115 V mV % % % % us us % us % s IVCC_FPWM IVCC_PS IVCC_SD IBST_FPWM EN_SKIP = 2.0 V, VFB forced above regulation point. DH, DL are open EN_SKIP = 5 V, VFB forced above regulation point, DH, DL are open EN_SKIP = L, VCC = 5 V, true shutdown EN_SKIP = 1.5 V, VFB forced above regulation point, DH and DL are open, No boost trap diode EN_SKIP = 5 V, VFB forced above regulation point, DH and DL are open No boost trap diode EN_SKIP = 0 V (Note 2) -10 1.5 1.5 2.5 2.5 1 0.3 mA mA uA mA VIN VCC 4.5 4.5 - 5.0 27 5.5 V V Symbol Test Conditions Min Typ Max Unit
IBST_PS
0.3
mA
IBST_SD dVCC/dt
1 10
mA V/ms
OVERCURRENT THRESHOLD DETECTION Total Detection Time OCSET Detection Time TDETECT T_OCDET A short period before SS (Note 2) 1.26 1.09 1.92 2.21 1.47 ms ms
2. Guaranteed by design, not tested in production.
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NCP5217A
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 5 V, TA = -40C to 85C, unless other noted)
Characteristics INTERNAL SOFT-START Soft-Start Time VOLTAGE ERROR AMPLIFIER DC Gain Unity Gain Bandwidth Slew Rate FB Bias Current Output Voltage Swing GAIN_VEA BW_VEA SR_VEA Ibias_FB Vmax_EA Vmin_EA DIFFERENTIAL CURRENT SENSE AMPLIFIER CS+ and CS- Common-mode Input Signal Range Input Bias Current Input Signal Range Offset Current at IDRP [(CS+) - (CS-)] to IDRP Gain VCSCOM_MAX CS_IIB CS_range IDRP_offset IDRP_GAIN (IDRP/((CS+) - (CS-))) BW_CS IDRP_Max IDRP_Min I_IDRP -1.0 (CS+) - (CS-) = 0 V (CS+) - (CS-) = 10 mV, V(IDRP) = 0.8 V TA = 25C TA=-40C to 85C Refer to AGND -100 -70 -1.0 0.475 0.425 20 2.5 0 35 0.525 3.5 100 70 1.0 0.575 0.625 MHz V V mA V nA mV mA mA/mV Isource_EA = 2 mA Isink_EA = 2 mA 3.3 3.5 0.15 0.3 (Note 2) (Note 2) COMP PIN TO GND = 100 pF (Note 2) 88 15 2.5 0.1 dB MHz V/ms mA V TSS 0.9 1.1 1.3 ms Symbol Test Conditions Min Typ Max Unit
Current-Sense Bandwidth Maximum IDRP Output Voltage Minimum IDRP Output Voltage IDRP Output current
At -3dB to DC Gain (Note 2) (CS+) - (CS-) = 70 mV, Isource drops to 95% of the value when V(IDRP) = 0.8 V
OVERCURRENT PROTECTION SETTING Overcurrent Threshold (OCTH) Detection Current Ratio of OC Threshold over OCSET Voltage OCSET Voltage for Default Fixed OC Threshold OCSET Voltage for Adjustable OC Threshold OCSET Voltage for OC Disable Default Fixed OC Threshold Adjustable OC Threshold I_OCSET Sourced from OCP before soft-start, Rocp = 16.7 kW is connected from OCP to AGND or FB V((CS+) - (CS-)) / V_OCSET (Note 2) Rocp v 2 kW is connected from OCP to AGND or FB Rocp = 8.3 ~ 25 kW is connected from OCP to AGND or FB Rocp w 35 kW is connected from OCP to AGND or FB (CS+) - (CS-), Pin IDRP/OCP is shorted to AGND or FB (CS+) - (CS-), During OC threshold, set a voltage at pin OCP VOCSET = 200 mV VOCSET = 600 mV 200 720 35 15 52 40 20 60 45 25 68 21.6 24 26.4 mA
K_OCSET VOCSET_DFT VOCSET_ADJ VOCSET_DIS V_OCTH_DFT V_OCTH ((CS+) - (CS-))
0.1 100 600
- mV mV mV mV mV
GATE DRIVERS DH Pull-HIGH Resistance DH Pull-LOW Resistance DL Pull-HIGH Resistance DL Pull-LOW Resistance RH_DH RL_DH RH_DL RL_DL 200 mA Source current 200 mA Sink current 200 mA Source current 200 mA Sink current 2.5 1.5 2 0.75 W W W W
2. Guaranteed by design, not tested in production.
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NCP5217A
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 5 V, TA = -40C to 85C, unless other noted)
Characteristics GATE DRIVERS DH Source Current DH Sink Current DL Source Current DL Sink Current Dead Time Isource_DH Isink_DH Isource_DL Isink_DL TD_LH TD_HL Negative Current Detection Threshold SWN source leakage Internal Resistor from DH to SWN CONTROL SECTION EN_SKIP Logic Input Voltage for Disable EN_SKIP Logic Input Voltage for FPWM EN_SKIP Logic Input Voltage for Skip Mode EN_SKIP Source Current EN_SKIP Sink Current PGOOD Pin ON Resistance PGOOD Pin OFF Current OUTPUT DISCHARGE MODE Output Discharge On-Resistance Threshold for Discharge Off TRE SETTING TRE Threshold Detection Current Detection Voltage for TRE Threshold Selection I_TRESET Source from DL in the short period before soft-start. (Rtre = 47 kW is connected from DL to GND Internal TRE_TH is set to 300 mV Internal TRE_TH is set to 500 mV TRE is Disabled (Note 2) (Note 2) Rtre w 75 kW (Note 2) Rtre = 44 ~ 50 kW (Note 2) Rtre v 25 kW (Note 2) 7.2 8 8.8 mA Rdischarge Vth_DisOff EN = 0 V 0.2 20 0.3 35 0.4 W V VEN_Disable Set as Disable Hysteresis VEN_FPWM VEN_SKIP Set as FCCM mode Set as SKIP Mode Hysteresis IEN_SOURCE IEN_SINK PGOOD_R PGOOD_LK VEN_SKIP = 0 V VEN_SKIP = 5 V I_PGOOD = 5 mA 100 1 0.7 150 1.7 2.35 100 1.0 200 1.95 2.6 175 1.3 250 2.25 2.85 250 0.1 0.1 V mV V V mV mA mA W mA NCD_TH ISWN_SD R_DH_SWN (Note 2) (Note 2) (Note 2) (Note 2) DL-off to DH-on (Note 2) DH-off to DL-on (Note 2) SWN-PGND, at EN_SKIP = 5 V EN_SKIP = 0 V (Note 2) 100 1 1.7 1.3 3.3 20 20 -1 1 mV uA kW A A A A ns Symbol Test Conditions Min Typ Max Unit
VDL_TRE_1 (Default) VDL_TRE_2 VDL_TRE_3
500 300 0
600
700 450 250
mV
TRE Comparator Offset Propagation Delay of TRE Comparator THERMAL SHUTDOWN Thermal Shutdown Thermal Shutdown Hysteresis
TRE_OS TD_PWM
10 20
mV ns
Tsd Tsdhys
(Note 2) (Note 2)
150 25
C C
2. Guaranteed by design, not tested in production.
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NCP5217A
TYPICAL OPERATING CHARACTERISTICS
0.83 0.82 VFB Vref VOLTAGE (V) 0.81 0.8 0.79 0.78 0.77 -40 200 150 100 50 0 -50 -100 -40
VCC PIN SHUTDOWN CURRENT (nA)
-15
10
35
60
85
-15
10
35
60
85
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
Figure 3. Vref Voltage vs Ambient Temperature
Figure 4. VCC Shutdown Current vs Ambient Temperature
0.8 0.7 IDRP_Gain (mA/mV) 0.6 0.5 0.4 0.3 0.2 -40
315 FSW SWITCHING FREQUENCY (kHz) 310 305 300 295 290 285 -40
-15
10
35
60
85
-15
10
35
60
85
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
Figure 5. Switching Frequency vs Ambient Temperature
40 BST PIN SHUTDOWN CURRENT (nA) 30 20 10 0 -10 -20 -40 DEFAULT FIX OC THRESHOLD (mV) 43 42 41 40 39 38
Figure 6. IDRP Gain vs Ambient Temperature
-15
10
35
60
85
37 -40
-15
10
35
60
85
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
Figure 7. BST Shutdown Current vs Ambient Temperature
Figure 8. Default Fix OC Threshold vs Ambient Temperature
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NCP5217A
TYPICAL OPERATING CHARACTERISTICS
Top to Bottom: EN, SWN, Vo, PGOOD
Top to Bottom: EN, SWN, Vo, PGOOD
Figure 9. Powerup Sequence
Figure 10. Powerdown Sequence
Top to Bottom: SWN_Slave, SWM, Vo
Top to Bottom: EN, SWM, Vo
Figure 11. On Line Mode Change (CCM " DCM)
Figure 12. On Line Mode Change (DCM " CCM)
Top to Bottom: SWN, Vo, Output Current
Figure 13. Typical Transient
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NCP5217A
DETAILED OPERATING DESCRIPTION
General
The NCP5217A synchronous step-down power controller contains a PWM controller for wide battery/adaptor voltage range applications The NCP5217A includes power good voltage monitor, soft-start, over current protection, under-voltage protection, overvoltage protection and thermal shutdown. The NCP5217A features power saving function which can increase the efficiency at light load. It is ideal for battery operated systems. The IC is packaged in QFN14.
Control Logic
further improve transient response in CCM, a transient response enhancement circuitry is implemented inside the NCP5217A. In CCM operation, the controller is continuously monitoring the COMP pin output voltage of the error amplifier to detect the load transient events. The functional block diagram of TRE is shown below.
COMP R C internal TRE_TH + +
TRE
The internal control logic is powered by VCC. The device is controlled by an EN_SKIP pin. The EN_SKIP serves two functions. When voltage of EN_SKIP is below VEN_Disable, it shuts down the device. When the voltage of EN_SKIP is between VEN_FPWM and VEN_SKIP, the device is operating as force PWM mode. When voltage level of EN_SKIP is above VEN_SKIP, the device is operating as power saving mode. When EN_SKIP is above VEN_Disable, the internal Vref is activated and power-on reset occurs which resets all the protection faults. Once Vref reaches its regulation voltage, an internal signal will wake up the supply under-voltage monitor which will assert a "GOOD" condition. In addition, the NCP5217A continuously monitors VCC level with an undervoltage lockout (UVLO) function.
Forced PWM Operation (FPWM Mode)
Figure 14. Block Diagram of TRE Circuit
The device is operating as force PWM mode if EN_SKIP voltage keeps at between VEN_FPWM and VEN_SKIP. Under this mode, the low-side gate driver signal is forced to be the complement of the high-side gate driver signal. This mode allows reverse inductor current, in such a way that it provides more accurate voltage regulation and better (fast) transient response. During the soft-start operation, the NCP5217A automatically runs as FPWM mode regardless of the EN_SKIP setting at either FPWM or SKIP mode to make sure to have smooth power up.
Pulse Skipping Operation (Skip Mode)
Once the large transient occurs, the COMP signal may be large enough to exceed the threshold and then TRE "flag" signal will be asserted in a short period which is typically around one normal switching cycle. In this short period, the controller will be running at high frequency and hence has faster response. After that the controller comes back to normal switching frequency operation. We can program the internal TRE threshold (TRE_TH). For detail please see the electrical table of "TRE Setting" section. Basically, the recommend internal TRE threshold value is around 1.5 times of peak-to-peak value of the COMP signal at CCM operation. The higher the internal TRE_TH, the lower sensitivity to load transient. The TRE function can be disable by setting the Rtre which is connecting to DL/TRE pin to less than 25 kW. For system component saving, it is usually set as default value, that is, Rtre is open (w75 kW) and internal TRE_TH is 300 mV typical.
The device is operating as skip mode if EN_SKIP voltage keeps above VEN_SKIP. However, in medium and high load range, the controller still runs in continuous-conduction-mode (CCM) of which it behaves exactly same as FPWM mode. In light load range, the controller will go to skip mode which is similar to conventional constant on-time scheme.
Transient Response Enhancement (TRE)
Top to Bottom SWN, Vo, Transient Signal
Figure 15. Transient Response with TRE Disable
For the conventional PWM controller in CCM, the fastest response time is one switching cycle in the worst case. To
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NCP5217A
The Figure 18 shows how to realize the AVP function. A current path is connecting to the FB pin via Rocp resistor. Rocp is not actually for AVP function, indeed, Rocp is used for OCP threshold value programming. The IDRP/OCP pin has dual functions: OCP programming and AVP. At the IDRP/OCP pin, conceptually there is a current source which is modulated by current sensing amplifier. The output voltage Vo with AVP is:
V O + V O0 * I O * R LL
(eq. 1)
Where Io is the load current, no load output voltage Vo0 is set by the external divider that is
Top to Bottom SWN, Vo, Transient Signal
V O0 + 1 )
Rt Rb
* V ref
(eq. 2)
Figure 16. Transient Response with TRE Enable Adaptive Voltage Positioning (AVP)
The load line impendence RLL is given by:
R LL + DCR * Gain_CS * Rt * Rs2 Rs1 ) Rs2
(eq. 3)
For applications with fast transient currents, adaptive voltage positioning can reduce peak-to-peak output voltage deviations due to load transients. With the use of AVP, the output voltage allows to have some controlled sag when load current is applied. Upon removal of the load, the output voltage returns no higher than the original level, just allowing one output transient peak to be cancelled over a load step up and release cycle. The amount of AVP is adjustable. The behaviors of the Vo waveforms with or without AVP are depicted at Figure 17.
Where DCR is inductor DC resistance. Gain_CS is a gain from [(CS+) - (CS-)] to IDRP Gain (At electrical table, the symbol is IDRP_GAIN), the typical value is 0.525 mA/mV. The AVP function can be easily disable by shorting the Rocp resistor into ground. From the equation we can see that the value of "top" resistor Rt can affect the RLL, so it is recommended to define the amount of RLL FRIST before defining the compensation component value. And if the user wants to fine tune the compensation network for optimizing the transient performance, it is NOT recommend to adjust the value of Rt. Otherwise, both transient performance and AVP amount will be affected. The following diagram shows the typical waveform of AVP. Note that the Rt typical value should be above 1 kW.
Vo With AVP Vo Without AVP
Figure 17. Adaptive Voltage Positioning
Vo Rt FB Rb Rocp IDRP/OCP L DCR Rs1 CS+ Cs Rs2 CS- + Gi + - Vref IDRP + COMP
Top to Bottom: SWN, Vo, Transient Signal (0.5-10-0.5A)
Figure 19. Typical waveform of AVP
Figure 18. Configuration for AVP function
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NCP5217A
Overcurrent Protection (OCP)
The NCP5217A protects power system if over current event occurs. The current is continuously monitored by the differential current sensing circuit. The current limit threshold voltage VOCSET can be programmed by resistor Rocset connecting at the IDRP/OCP pin. However, fixed default VOCSET can be achieved if Rocset is less than 2 kW. If the inductor current exceeds the current threshold continuously, the top gate driver will be turned off cycle by cycle. If it happens over consecutive 16 clock cycles time (16 x 1/fSW), the device is latched off such that top and bottom gate drivers are off. EN resets or power recycle the device can exit the fault. The following diagram shows the typical behavior of OCP.
It should be noted that there are two configurations for Rocp resistor. If Adaptor Voltage Position (AVP) is used, the Rocp should be connected to FB pin. If AVP is not used, the Rocp should be connected to ground. At the IDRP/OCP pin, there is a constant current(24 mA typ.) flowing out during the programming stage at system start up. This is used to sense the voltage level which is developed by a resistor Rocp so as to program the overcurrent detection threshold voltage. For typical application, the Vocth is set as default value (40 mV typ) by setting Rocp = 0 W, or directly short the IDRP/OCP pin to ground. It has the benefit of saving one component at application board. For other programming values of Vocth, please refer to the electrical table of "Overcurrent Protection Setting" section.
Guidelines for selecting OCP Trip Component
1. Choose the value of Rocp for Vocth selection. (typical is 0 W for Vocth = 40 mV typical) 2. Define the DC value of OCP trip point (IOCP_DC) that you want. The typical value is 1.5 to 1.8 times of maximum loading current. For example, if maximum loading is 10 A, then set OCP trip point at 15 A to 18 A. 3. Calculate the inductor peak current (Ipk)which is estimated by the equation:
I pk + I OCP_DC )
Top to Bottom : SWN, Vo, PGOOD, Io
V O * (V IN * V O) 2 * V IN * f SW * L O
(eq. 4)
Figure 20. Overcurrent Protection
4. Check with inductor datasheet to find out the value of inductor DC resistance DCR, then calculate the RS1, RS2 dividing factor k based on the equation:
k+ V OCth I pk * DCR
(eq. 5)
The NCP5217A uses lossless inductor current sensing for acquiring current information. In addition, the threshold OCP voltage can be programmed to some desired value by setting the programming resistor Rocp.
Vo Rt Rb + - Vref IDRP
5. Select Cs value between 100 nF to 200 nF. Typically, 100 nF will be used. 6. Calculate Rs1 value by the equation:
Rs1 + L k * DCR * Cs k * Rs1 1*k
(eq. 6)
FB
+
COMP
7. Calculate Rs2 value by the equation:
Rs2 +
(eq. 7)
IDRP/OCP L DCR Rs1 Cs Rocp CS+ Rs2 CS-
+
Gi
Without AVP Vo Rt Rb Rocp IDRP/OCP L DCR Rs1 Cs Rs2 CS+ CS- + + - Vref IDRP
8. Hence, all the current sense components Rs1, Rs2, Cs have been found for target IOCP_DC. 9. If Rs2 is not used (open), set k = 1, at that moment, the Ipk will be restricted by:
COMP
FB
+
I pk +
V OCth DCR
(eq. 8)
Overvoltage Protection (OVP)
Gi
Figure 21. OCP Configurations
With AVP
When VFB voltage is above 115% (typical) of the nominal VFB voltage for over 1.5 ms blanking time, an OV fault is set. At that moment, the top gate drive is turned off and the bottom gate drive is turned on until the VFB below lower under voltage (UV) threshold and bottom gate drive is
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NCP5217A
turned on again whenever VFB goes above upper UV threshold. EN resets or power recycle the device can exit the fault. The following diagram shows the typical waveform when OVP event occurs. consecutive 8 clock cycles, an UV fault is set and the device is latched off such that both top and bottom gate drives are off. EN resets or power recycle the device can exit the fault.
Top to Bottom : SWN, Vo, PGOOD Top to Bottom : SWN, DL, Vo, PGOOD
Figure 23. Undervoltage Protection Thermal Shutdown
Figure 22. Overvoltage Protection Undervoltage Protection (UVP)
An UVP circuit monitors the VFB voltage to detect under voltage event. The undervoltage limit is 80% of the nominal VFB voltage. If the VFB voltage is below this threshold over
+5V V5 PGND R1 R11 1 R2 2 U1 1 EN_SKIP 2 CS+ 3 CS-/Vo NCP5217A 4 COMP 5 FB 6 PGOOD C4 R7 R9 R8 AGND AGND 7 14 BST DH 13 SWN 12 IDRP/OCP 11 VCC 10 C6 R17 R18 R16 R10 R13 C20 R14 OFF = Skip Mode 1-2 = FCCM Mode EN_SKIP 3-2 = Disable C5 D1 R12
The IC will shutdown if the die temperature exceeds 150C. The IC restarts operation only after the junction temperature drops below 125C.
C7 C8 C9 C11 VIN M1 M2 L1 C14 C15 C17 C18 D3 VOUT PGND BNC1 PGND R21 D2 VIN_GND
3 SW1
+5V J1 Default = Close J1 R3 LED1 M5 R4 R5 LED2
C1 J100 Default = Open J100 COMP C2 R6 C3 PGOOD
J2 R15 1 2 3 1-2 = OCP Only 3-2 = OCP + AVP M3
R19 M4 C10
R20
DL/TRESET 9 PGND 8
AGND
PGND
Figure 24. Demo Board Schematic
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NCP5217A
DEMO BOARD BILL OF MATERIAL BOM (See next tables for compensation network and power stage)
Designator U1 R1 R2 R3, R4 R5 R10 R11 R12 R13, R14, R15, R17 R16, R18, R21, C1 C5, C6 C7,C8,C9, C11 C10, C13, C17, C18 C20 D1 D2, D3 M5 LED1 LED2 J1, J100, COMP, EN_SKIP, PGOOD, AGND V5, VIN, VIN_GND, PGND, PGND, PGND, VOUT BNC1 SW1 Qty 1 1 1 2 1 1 1 1 4 3 1 2 4 4 1 1 1 1 1 1 6 Description Single Synchronous Stepdown Controller Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% Chip Resistor, $5% - MLCC Chip Capacitor, $10% Temp Char: X7R, Rate V = 50 V MLCC Chip Capacitor, $20% Temp Char: X5R, Rate V=25V MLCC Chip Capacitor, $20% Temp Char: X5R, Rate V = 25 V - MLCC Chip Capacitor, $20% Temp Char: X7R, Rate V = 50 V 30V Schottky Diode Vf=0.35V @ 10mA - Power MOSFET 50 V, 200 mA Single N-Channel Surface Mount LED (Green) Surface Mount LED (Red) Pin Header Single Row Value - 75k 10k 1k 100k 5.6 20k 5.6 0 DNP 100 nF 1 mF 4.7 mF DNP 0.1 mF - DNP - - - - Footprint QFN14 (Special) 0603 0603 0603 0603 0603 0603 0603 0603 - 0603 0805 0805 - 0603 SOT-23 - SOT-23 0805 0805 Pitch=2.54 mm Manufacturer ON Semiconductor Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic - Panasonic Panasonic Panasonic - Panasonic ON Semiconductor - ON Semiconductor LUMEX LUMEX Betamax Manufacturer P/N NCP5217MNR2G ERJ3GEYJ753V ERJ3GEYJ103V ERJ3GEYJ102V ERJ3GEYJ104V ERJ3GEYJ5R6V ERJ3GEYJ203V ERJ3GEYJ5R6V ERJ3GEYJR00V - ECJ1VB1E104K ECJ2FB1E105M ECJ2FB1E475M - ECJ1VB1E104M BAT54LT1 - BSS138L SML-LX0805GC-TR SML-LX0805IC-TR 2211S-40G-F1
7
Terminal Pin
-
f = 1.74 mm
HARWIN
H2121-01
1 1
SMB SMT Straight Socket 2P ON-OFF-ON toggle switch
- -
5.1 x 5.1 mm 3 pins, 2.54 mm pitch
Tyco Electronics C&K
RS Stock# 420-5401 RS Stock# 249-2984 Manufacturer # 7203SYCQE
http://onsemi.com
13
NCP5217A
DEMO BOARD BILL OF MATERIAL (Vo = 1.1 V, Io = 15 A)
Item Component R6 R7 R8 Compensation Network R9 C2 C3 C4 M1, M2 M3, M4 L1 Power Stage & Current Sense R19 R20 C14, C15 Value 100k 560 3k 8k 470 pF 15 pF 1.2 nF - - 1 mH 6.2k 9.1k 330 mF 6 mW Tol 1% 1% 1% 1% 10% 10% 10% - - 20% 1% 1% 20% Footprint 0603 0603 0603 0603 0603 0603 0603 SOIC8-FL SOIC8-FL 10x11.5mm 0603 0603 7343 Manufacturer Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic ON Semiconductor ON Semiconductor Cyntec Panasonic Panasonic Panasonic Sanyo Manufacturer P/N ERJ3EKF1003V ERJ3EKF5600V ERJ3EKF3001V ERJ3EKF8001V ECJ1VC1H471K ECJ1VC1H150K ECJ1VB1H122K NTMFS4821N NTMFS4847N PCMC104T-1R0MN ERJ3EKF6201V ERJ3EKF9101V EEFSX0D331XR 2TPLF330M6
DEMO BOARD BILL OF MATERIAL (Vo = 1.5 V, Io = 8 A)
Item Component R6 R7 R8 Compensation Network R9 C2 C3 C4 M1, M3 Power Stage & Current Sense M2, M4 L1 R19 Power Stage & Current Sense R20 C14, C15 Value 82k 1k 5k 5.71k 270 pF 15 pF 560 pF - DNP 1 mH 4.3k DNP 220 mF 12 mW Tol 1% 1% 1% 1% 10% 10% 10% - - 20% 1% - 20% Footprint 0603 0603 0603 0603 0603 0603 0603 SO8 - 10x11.5mm 13x14x4.9mm 0603 - 7343 Manufacturer Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic ON Semiconductor - Cyntec WE Panasonic - Panasonic Sanyo Manufacturer P/N ERJ3EKF8202V ERJ3EKF1001V ERJ3EKF5001V ERJ3EKF5711V ECJ1VC1H271K ECJ1VC1H150K ECJ1VB1H561K NTMS4705N - PCMC104T-1R0MN 744315120 ERJ3EKF4301V - EEFUD0D221XR 2R5TPL220MC
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14
NCP5217A
DEMO BOARD BILL OF MATERIAL (Vo = 1.8 V, Io = 8 A)
Item Component R6 R7 R8 Compensation Network R9 C2 C3 C4 M1, M3 M2, M4 L1 Power Stage & Current Sense R19 R20 C14, C15 Value 150k 1k 5k 4K 220pF 18pF 560pF - DNP 1.2uH 4.3K DNP 220uF 12mW Sanyo 2R5TPL220MC Tol 1% 1% 1% 1% 10% 10% 10% - - 20% 1% - 20% Footprint 0603 0603 0603 0603 0603 0603 0603 SO8 - 10x11.5mm 0603 - 7343 Manufacturer Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic ON Semi - TOKO Panasonic - Panasonic Manufacturer P/N ERJ3EKF1503V ERJ3EKF1001V ERJ3EKF5001V ERJ3EKF4001V ECJ1VC1H221K ECJ1VC1H180K ECJ1VB1H561K NTMS4705N - FDA1254-1R2M=P3 ERJ3EKF4301V - EEFUD0D221XR
http://onsemi.com
15
NCP5217A
PACKAGE DIMENSIONS
QFN14 3.5x3.5, 0.5P CASE 485AL-01 ISSUE O
D A B L1 E
OPTIONAL PIN CONSTRUCTION EDGE OF PACKAGE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e e2 K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.50 BSC 1.90 2.15 3.50 BSC 1.90 2.15 0.50 BSC 1.50 BSC 0.20 --- 0.30 0.50 0.00 0.03
L
L
PIN 1 LOCATION
2X 2X
0.15 C 0.15 C 0.10 C TOP VIEW (A3) A 0.08 C
NOTE 4 DETAIL B DETAIL A
SIDE VIEW D2
7 9
A1
C
SEATING PLANE
14X
K
14X
L
E2 e
2 1 14
14X
b 0.10 C A B 0.05 C
NOTE 3
e2 BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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16
EEE EEE EEE
DETAIL B
2X
CCC CCC CCC
DETAIL A
DETAIL A
OPTIONAL PIN CONSTRUCTION
EXPOSED Cu
MOLD CMPD
OPTIONAL PIN CONSTRUCTION
SOLDERING FOOTPRINT*
3.80 14X 0.63
2X
14X
0.36
2.12 0.50 PITCH 1.50 PITCH
DIMENSIONS: MILLIMETERS
NCP5217A/D

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